A current trend in modern radio design is the attempt to continually increase the level of integration. A problem arises, however, in that the required die area increases as more and more functions are integrated into single chip radio designs. An example is the DRP based cellular phones which incorporate other radios in addition to the basic cellular radio, including Bluetooth, GPS, FM, etc. As more and more functions are added, interference between the various radios (which run at different frequencies) is becoming more and more of a problem. As physical distances decrease between radios and IC pins get closer to each other frequency planning is becoming more difficult on system on chip (SoC) designs. For example, the physical distance between the digitally-controlled crystal oscillator (DCXO) pin and the transmit RF output is becoming smaller and thus is more susceptible to interference caused by the RF output signal being coupled into the reference frequency input which should be the purest signal in the circuit. This contaminated signal then passes through a slicer (a very nonlinear circuit which creates harmonics). At certain harmonics (i.e., integer ratio of output RF signal to reference signal), subharmonic mixing of the RF output signal with the reference frequency signal occurs in the slicer. A portion of the mixing products are close to DC which is likely to be within the bandwidth of the PLL thus degrading its performance and impacting the quality of the RF output signal. The RF output signal coupled back to the DCXO manifests itself as jitter in the reference frequency, i.e., modulation of the zero crossings of the frequency reference signal which, for integer or near-integer ratios of RF output (normally modulated) and reference frequency, is within the loop bandwidth resulting in degraded phase error.
A diagram illustrating a first example prior art single chip polar transceiver radio showing a transmitter incorporating an all-digital phase-locked loop (ADPLL)-based transmitter circuits, as well as potential parasitic coupling paths is shown in FIG. 1. The single chip radio, generally referenced 10, comprises an ADPLL circuit 16, pulse shaping filter 12, amplitude modulation (AM) circuit 14, digital RF to amplitude converter (DRAC) 18 (also referred to as a Digitally Controlled Power Amplifier or DPA) which consists of a Pre Power Amplifier (PPA) and Sigma-Delta Amplitude Modulator (SAM), digitally controlled crystal oscillator (DCXO) 20 and slicer 25. The ADPLL 16 comprises modulating FCW adder 11, reference phase accumulator 15, time to digital converter (TDC) 13, subtracter/adder 17, loop filter 21, modulating adder 23, DCO Gain Multiplier 9 and digitally controlled oscillator (DCO) 27.
The radio implements a direct FM or polar transmitter whereby the ADPLL generates an output frequency in accordance with a frequency control word (FCW) input. The CKV clock signal output of the ADPLL is amplitude modulated in accordance with an amplitude control word (ACW) generated by the AM circuit 14.
Depending on the particular implementation of the radio, a potential problem that may occur is excessive RMS phase error, or phase/frequency modulation distortion in general, for “integer-N channels” of transmission. The integer-N channels are those for which the ratio between the carrier frequency produced by the ADPLL is an integer multiple of the input reference frequency FREF. In a highly integrated multi-band cellular radio with its reference clock generating Digitally-Controlled Crystal Oscillator (DCXO) also being integrated in the same die, a significant performance degrading phenomenon is the coupling of the RF transmit output signal through the crystal pins or the buffer of the DCXO.
Thus, the RMS phase error problem is due to the RF output or internal RF (e.g., digital RF) signal coupling back into the DCXO or its buffer that provides the frequency reference signal for the local oscillator based on the ADPLL. The much higher frequency RF output signal that is generated is coupled into the much lower frequency FREF input, where a slicer exists to convert the oscillations into a two-level clock signal. The slicer performs a non-linear operation which allows the additive interference to translate into additive phase (or jitter) on the clock produced by this circuit. It is noted that this problem can arise in any type of PLL or frequency synthesizer circuit, where the output RF signal has the opportunity of coupling into the FREF circuitry, as typically is the case in a system-on-chip (SoC) environment.
The coupling mechanism is modeled in FIG. 1 as a modulus CKV/FREF block 26 coupled to a gain block 24. This interference signal is coupled to the FREF signal via virtual adder 22 before it enters the slicer 25. Thus, the frequency reference signal output of the slicer contains this interference signal. Thus, the ADPLL output, derived signals or the RF output signal is effectively coupled (various paths are indicated by dotted lines 28 and 29) from the output of the transmitter back to the frequency reference input. This coupling creates subharmonic mixing in the slicer (i.e. the buffer circuit following the DCXO core) through its nonlinear devices. The in-band spurs contaminated with the modulated TX signal generated through this mixing phenomenon pass through the ADPLL, being within the loop bandwidth, and degrade the phase error performance of the transmitter.
The RF interference at the DCXO is detrimental to the performance of the radio at integer-N channels because it gets downconverted to zero (due to being located at an integer multiple of the frequency reference), where it creates slow jitter on the frequency reference output of the slicer, via the AM/PM occurring in the slicer. The slow jitter passes through the low-pass frequency response of the PLL and reaches the output, thereby distorting the modulation (e.g., degrading the phase-trajectory error in GSM).
In highly integrated small silicon area radios, such as multi-band cellular radios with integrated RF and digital baseband (DBB), with very short separation between the RF and FREF bond pads, bond wires, balls and pins, this problem is practically unavoidable.
A block diagram illustrating an example prior art conventional single chip radio transceiver incorporating an on-chip DCXO buffer and showing a potential parasitic coupling path is shown in FIG. 2. Note that for clarity, only the transmitter and related phase locked loop's portions of the radio are shown. The circuit shown illustrates the source of the interference phenomena in a generic transmitter that utilizes an offset-PLL up-conversion modulation loop, widely used in GSM transceivers.
The transmitter part of the radio, generally referenced 130, comprises a DCXO 158 coupled to a crystal 154, slicer 160, IF PLL 162, RF PLL 164, offset mixer 148, low pass filter (LPF) 152, 90 degree phase shift 166, I mixer 132, Q mixer 134, summer 136, phase/frequency detector (PFD) 138, low pass loop filter 140, voltage controlled oscillator (VCO) 142 and pre-power amplifier (PPA) 144.
Consider the I/Q based transmitter a part of an integrated multi-band cellular radio with an on-chip DCXO coupled to the external crystal 154 at pin 156. The local oscillator (LO) signal or transmit RF output signal at pin 146 is coupled through the crystal pins back to the input of the DCXO, as indicated by dotted line 150. The coupling path may be via on-chip pathways, off-chip pathways (i.e. bond wires, pins, PCB wiring, etc.) or any combination thereof.
As in the radio of FIG. 1, this coupling creates sub-harmonic mixing in the slicer (i.e. the DCXO buffer) through the nonlinear devices making up the slicer. This results in in-band frequency spurs contaminated with modulated TX RF output signal which pass though the PLL resulting in degraded TX phase error performance.
Aside from the interference problem described above, an additional problem in an ADPLL based transmitter such as the one shown in FIG. 1 arises due to the finite resolution of the TDC (approximately 20 picoseconds, i.e. an inverter delay) which creates dead-beat effects at certain channels (i.e. integer-N and neighboring frequencies). This also degrades the modulation quality of the transmitter.
There have been prior art attempts to solve the above described problems. One such solution is described in U.S. application Ser. No. 11/853,182, filed Sep. 11, 2007, entitled “Adaptive Spectral Noise Shaping To Improve Time To Digital Converter Quantization Resolution Using Dithering,” incorporated herein by reference in its entirety. In this solution, the circuitry of the TDC was modified to perform a reference frequency (FREF) clock delay shift through digital control of a capacitive load. A disadvantage of this approach, however, is that it created excessive transition times (e.g., more than 300 picoseconds), which created increased sensitivity to noise pickup by tying the delay generation through the degradation in the transition time. It is advantageous to have fast transition edges in order to minimize the duration in the metastable region between the legal logic levels to minimize noise pick-up.
Another prior art solution is described in U.S. application Ser. No. 11/832,292, filed Aug. 1, 2007, entitled “Minimization Of RMS Phase Error In A Phase Locked Loop By Dithering Of A Frequency Reference,” incorporated herein by reference in its entirety. In this solution, magnetic coupling through the chip bond wires is used to introduce intentional dithering to the DCXO input. This approach, however, is not well controllable in both the amplitude and frequency location. It represents a more “brute force” approach which radiates the dithering energy into other circuits which is likely to cause one or more other unintended consequences.
There is thus a need for a mechanism that addresses these two problems and that is capable of (1) mitigating or eliminating the effects of the interference caused by coupling of the transmit RF output signal, or internal signals derived from the DCO, back into the frequency reference input to the ADPLL based local oscillator in a controllable manner, (2) overcoming continued scaling of problem as more coupling is inevitable as radio integration and scaling advance, and (3) permitting the increased use of digitization in radio design (such as the use of a TDC in place of a traditional charge-pump phase/frequency detector).